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This version: Mar. 6. 2000 Previous version: Mar. 8. 1999
Semiconductor MSC23437D-xxBS9/DS9
4,194,304-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23437D-xxBS9/DS9 is a 4,194,304-word x 36-bit CMOS dynamic random access memory module which is composed of nine 16Mb DRAMs (4Mx4) in SOJ packages mounted with nine decoupling capacitors. This is a 72-pin single in-line memory module. This module supports any application where high density and large capacity of storage memory are required.
FEATURES
* 4,194,304-word x 36-bit organization (ECC) * 72-pin Single In-Line Memory Module MSC23437D-xxBS9 : Gold tab MSC23437D-XXDS9 : Solder tab * Single 5V power supply, 10% tolerance * Input : TTL compatible * Output : TTL compatible, 3-state * Refresh : 4096cycles/64ms * Fast page mode, read modify write capability * /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability * Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.) tRAC MSC23437D-60BS9/DS9 MSC23437D-70BS9/DS9 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns tOEA 15ns 20ns Cycle Time (Min.) 110ns 130ns Power Dissipation (Max.) Operating 3465mW 3218mW Standby 49.5mW
Family
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MODULE OUTLINE
MSC23437D-xxBS9/DS9
107.950.2*1 101.19Typ. (Unit : mm) 5.28Max.
3.38Typ.
3.18 25.40.2
10.16Typ.
6.35Typ.
1 1.270.1 R1.57 6.35 95.25 1.04Typ.
72
2.03Typ. 6.35Typ.
+0.1 1.27 -0.08
Note: 1. Tolerance over 12.5mm from board edge is 0.5.
3.5Min.
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Presence Detect Pins Pin No. 67 68 69 70 11 Pin Name PD1 PD2 PD3 PD4 PD5 -60 VSS NC NC NC VSS -70 VSS NC VSS NC VSS Pin Name VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name /OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 NC NC DQ17 DQ18 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin Name DQ19 DQ20 VSS /CAS0 A10 A11 NC /RAS0 NC DQ21 /WE VSS DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 NC NC NC PD1 PD2 PD3 PD4 NC VSS
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BLOCK DIAGRAM
A0-A11 /RAS0 /CAS0 /WE /OE A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D0 VCC VSS DQ0 DQ1 DQ2 DQ3 A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D5 VCC VSS DQ20 DQ21 DQ22 DQ23
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D1 VCC VSS A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D2 VCC VSS
DQ4 DQ5 DQ6 DQ7
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D6 VCC VSS
DQ24 DQ25 DQ26 DQ27
DQ8 DQ9 DQ10 DQ11
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D7 VCC VSS
DQ28 DQ29 DQ30 DQ31
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D3 VCC VSS
DQ12 DQ13 DQ14 DQ15
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D8 VCC VSS
DQ32 DQ33 DQ34 DQ35
A0-A11 DQ /RAS DQ /CAS DQ /WE DQ /OE D4 VCC VSS
DQ16 DQ17 DQ18 DQ19
VCC VSS C0-C8
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD * TOPR TSTG *: Ta = 25C Rating -0.5 to 7.0 50 9 0 to 70 -40 to 125 Unit V mA W C C
Recommended Operating Conditions (Ta = 0C to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -0.5 Typ. 5.0 0 Max. 5.5 0 VCC + 0.5 0.8 Unit V V V V
Capacitance (VCC = 5V 10%, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A11) Input Capacitance (/RAS0, /CAS0, /WE, /OE) I/O Capacitance (DQ0 - DQ35) Symbol CIN1 CIN2 CI/O Typ. Max. 64 73 16 Unit pF pF pF
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DC Characteristics (VCC = 5V 10%, Ta = 0C to 70C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -5.0mA IOL = 4.2mA 0V VIN 6.5V; All other pins not under test = 0V DQ disable 0V VOUT VCC /RAS, /CAS cycling, tRC = Min. /RAS, /CAS = VIH Power supply current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode) ICC2 /RAS, /CAS VCC - 0.2V /RAS cycling, /CAS = VIH, tRC = Min. /RAS cycling, /CAS before /RAS /RAS = VIL, /CAS cycling, tPC = Min. -60 Min. 2.4 0 -90 Max. VCC 0.4 90 Min. 2.4 0 -90 -70 Max. VCC 0.4 90 Unit V V A Note
Output Leakage Current Average Power Supply Current (Operating)
ILO
-10
10
-10
10
A
ICC1

630 18 9

585 18 9
mA
1, 2
mA
1
ICC3
630
585
mA
1, 2
ICC6
630
585
mA
1, 2
ICC7
585
540
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH.
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AC Characteristics (1/2) (VCC = 5V 10%, Ta = 0C to 70C) Note: 1, 2, 3, 11, 12 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Access Time from /OE Output Low Impedance Time from /CAS /CAS to Data Output Buffer Turn-off Delay Time /OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode) /RAS Hold Time /RAS Hold Time referenced to /OE /CAS Precharge Time (Fast Page Mode) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH -60 Min. 110 155 40 85 0 0 0 3 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 15 30 0 0 0 Max. 60 15 30 35 15 15 15 50 64 10K 100K 10K 45 30 Min. 130 185 45 100 0 0 0 3 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 15 35 0 0 0 -70 Max. 70 20 35 40 20 20 20 50 64 10K 100K 10K 50 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 Note
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AC Characteristics (2/2) (VCC = 5V 10%, Ta = 0C to 70C) Note: 1, 2, 3, 11, 12 Parameter Write Command Set-up Time Write Command Hold Time Write Command Pulse Width /OE Command Hold Time Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /OE to Data-in Delay Time /CAS to /WE Delay Time Column Address to /WE Delay Time /RAS to /WE Delay Time /CAS Precharge /WE Delay Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time from /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode) Symbol tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH -60 Min. 0 10 10 15 15 15 0 10 15 40 55 85 60 5 10 10 10 10 10 10 Max. Min. 0 15 10 20 20 20 0 15 20 50 65 100 70 5 10 10 10 10 10 10 -70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 Note 9
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Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 5ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictve operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD(Min.), tRWD tRWD(Min.), tAWD tAWD(Min.) and tCPWD tCPWD(Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE leading edge in an /OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS only refresh or /CAS before /RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
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